1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor devices and, more particularly, to the manufacture of semiconductor devices having both high-performance CMOS devices and high-performance bipolar devices integrated on a single chip at high density.
2. Description of the Prior Art
High density integrated circuits have been known and used for a number of years. Such devices have typically utilized single technologies through the chip on which they are integrated. In the course of this development, high density integration as well as designs for extremely high performance devices have been designed and manufactured. However, more recently, it has become desirable to use different technologies on the same chip in order to exploit particular performance characteristics of a particular technology which are unavailable in other technologies (e.g., high speed from bipolar devices and low power requirements from CMOS).
While there has been some success in achieving integrated circuit devices which combine several technologies such as CMOS circuits, including, as well, individual NMOS and PMOS transistors and other circuit elements, and bipolar transistors, the integrated circuits which have been realized have required trade-offs between complexity of manufacture, density of integration and performance of the individual circuits and transistors in the integrated circuit.
In particular, CMOS circuits formed by the LDD process as disclosed more fully in Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology, by Tsang et al, IEEE Transactions of Electron Devices, Vol. ED-29, No. 4, pp.590-596, April, 1982, (which is co-authored by two of the joint inventors of the present invention and hereby fully incorporated by reference) and bipolar transistors formed by the self-aligned polybase/polyemitter technology, disclosed more fully in Self-Aligned Bipolar Transistors for High-Performance and Low-Power-Delay VLSI, by T. H. Ning et al, IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, September 1981, which is also hereby fully incorporated by reference, are extremely high-performance devices which have presented unusual difficulties in integration on a common chip without degrading performance of one or both types of devices. The CMOS process provides circuits with high performance structures such as lightly doped drain (LDD) formations and channel lengths of less than 1.0 .mu.m and the self-aligned double poly bipolar transistors exhibit cut-off frequencies of about 20 GHz. Therefore it is particularly desirable that these devices be integrated on the same chip at high density while retaining all of the above performance characteristics. At the same time, it is important that the process by which such high density integration of these devices is achieved not render such integrated circuits economically unfeasible due to the complexity of the process and reduced manufacturing yields corresponding to such complexity. In this regard, prior art approaches such as that disclosed in Schaber, U.S. Pat. No. 4,752,589, provide process steps which "decouple" the formation of the CMOS transistors and the bipolar transistors and having a minimum number of process steps which are common to both the Bipolar and CMOS transistors. In Schaber, for example, evidently only a two layer gate electrode is formed concurrently with the emitter and collector zone of the bipolar transistor in order to decouple the phosphorus doping of the MOS gates and the arsenic doping of the polysilicon emitters; the process increasing the overall number of elements of the transistors which are formed and the overall number of process steps.
It has also been characteristic of the prior art, when integrated circuits utilizing plural technologies are manufactured, to manufacture each type of device in fairly complete sub-processes, thus separating the processes corresponding to each technology. Accordingly, while so-called self-aligned and self-masking techniques are known, for the purpose of reducing the number of necessary masks and processing steps and increasing manufacturing yields, such techniques have not been greatly utilized in forming integrated circuits comprising plural technologies. Further, known techniques for forming integrated circuits have not utilized processing steps common to both technologies for simultaneously forming portions of transistors and other elements in the different technologies. Similarly, prior integrated circuits utilizing plural technologies often form the devices of each technology at different levels within or above the substrate, complicating wiring and manufacturing processes necessary to complete such wiring.